paramset: A Verilog-A/MS Implementation of Spice .model Statements

Version 5, December 2004 The promise that comes from supporting compact modeling in Verilog-A/MS is the release of the designers from the tyranny of proprietary models. However, that promise is only half satisfied if we only support the model equations in Verilog-A/MS. While having a industry standard language for expressing model equations is critically important, it does not address the problem of proprietary .model files. To completely fulfill the promise, we must provide non-proprietary industry standard equivalents to all of the capabilities currently used in SPICE .model files. That includes support for the .model statements themselves, plus support for process corners, Monte Carlo analysis, etc.